The terms “metal-oxide-semiconductor” (MOS) and “complementary metal-oxide-semiconductor” (CMOS) are widely used to refer to insulated gate field effect transistors (IGFETs) employing any type of gate conductor, not just metals, and any type of gate insulator, not just oxides, and such broader usage is intended herein.
It is known that CMOS devices are subject to “latch-up”, a phenomenon wherein under certain operating conditions, the CMOS device can switch from normal operation to a persistent conductive state that is insensitive to the input voltage applied to the control terminal of the CMOS device. Often, latch-up can only be relieved by interrupting the power supply to the CMOS device which, if undamaged, may recover and resume normal operation. Latch-up arises as a consequence of the parasitic NPN and PNP bipolar transistors that are inherent in the CMOS device structure (e.g., see FIG. 1). Many events such as voltage transients, radiation, increasing temperature, and so forth, can trigger latch-up and much effort has been expended in trying to make CMOS devices more robust in their ability to resist latch-up without adverse effect on other device properties. This has proved to be a difficult problem, especially as CMOS device dimensions have been shrunk for use in ever denser and more complex ICs. An especially persistent problem has been latch-up temperature sensitivity. Other things being equal, as device temperature increases, latch-up becomes more likely, which is undesirable. Thus, there is an ongoing need to improve CMOS latch-up robustness for higher device temperatures.